71. G. S. Lin and you will J. B. Kuo, “Fringing-Caused Slim-Channel-Effect (FINCE) Related Capacitance Decisions from Nanometer FD SOI NMOS Products Having fun with Mesa-Isolation Via three dimensional Simulation” , EDSM , Taiwan ,
72. J. B. Kuo, “Evolution from Bootstrap Approaches to Low-Current CMOS Electronic VLSI Circuits to own SOC Programs” , IWSOC , Banff, Canada ,
P. Yang, “Door Misalignment Impression Related Capacitance Decisions away from good 100nm DG FD SOI NMOS Unit that have letter+/p+ Poly Most useful/Bottom Gate” , ICSICT , Beijing, China
73. G. Y. Liu, Letter. C. Wang and you will J. B. Kuo, “Energy-Efficient CMOS High-Stream Driver Routine to the Subservient Adiabatic/Bootstrap (CAB) Technique for Reasonable-Stamina TFT-Lcd Program Applications” , ISCAS , Kobe, Japan ,
74. Y. S. Lin, C. H. Lin, J. B. Kuo and you may K. W. Su, “CGS Capacitance Event from 100nm FD SOI CMOS Products which have HfO2 High-k Gate Dielectric Offered Vertical and Fringing Displacement Effects” , HKEDSSC , Hong-kong ,
75. J. B. KUo, C. H. Hsu and you may C. P. Yang, “Gate-Misalignment Relevant Capacitance Conclusion of a beneficial 100nm DG SOI MOS Gizmos with N+/p+ Top/Bottom Gate” , HKEDSSC , Hong-kong ,
76. Grams. Y. Liu, N. C. Wang and J. B. Kuo, “Energy-Efficient CMOS Large-Stream Rider Routine towards Subservient Adiabatic/Bootstrap (CAB) Way of Low-Energy TFT-Liquid crystal display System Applications” , ISCAS , Kobe, The japanese ,
77. H. P. Chen and you may J. B. Kuo, “An effective 0.8V CMOS TSPC Adiabatic DCVS Reasoning Circuit into the Bootstrap Techniques to have Lower-Energy VLSI” , ICECS , Israel ,
B. Kuo, “A manuscript 0
80. J. B. Kuo and you can H. P. Chen, “A minimal-Current CMOS Load Driver towards Adiabatic and Bootstrap Approaches for Low-Energy Program Applications” , MWSCAS , Hiroshima, Japan ,
83. Yards. T. Lin, E. C. Sunlight, and J. B. Kuo, “Asymmetric Door Misalignment Affect Subthreshold Qualities DG SOI NMOS Devices Offered Fringing Electric Field effect” , Electron Gizmos and Question Symposium ,
84. J. B. Kuo, Elizabeth. C. Sunshine, and you will Meters. T. Lin, “Data regarding Entrance Misalignment Affect the brand new Tolerance Current off Double-Entrance (DG) Ultrathin FD SOI NMOS Devices Playing with a tight Jackson, MN women date site Design Considering Fringing Electronic Field effect” , IEEE Electron Devices getting Microwave and you can Optoelectronic Applications ,
86. Elizabeth. Shen and you may J. 8V BP-DTMOS Articles Addressable Memories Telephone Routine Based on SOI-DTMOS Procedure” , IEEE Meeting into the Electron Gizmos and you can Solid-state Circuits , Hong-kong ,
87. P. C. Chen and J. B. Kuo, “ic Reason Circuit Playing with a direct Bootstrap (DB) Technique for Reasonable-voltage CMOS VLSI” , Global Symposium with the Circuits and Systems ,
89. J. B. Kuo and S. C. Lin, “Lightweight Dysfunction Model to own PD SOI NMOS Equipment Considering BJT/MOS Impact Ionization for Liven Circuits Simulation” , IEDMS , Taipei ,
ninety. J. B. Kuo and you can S. C. Lin, “Compact LDD/FD SOI CMOS Equipment Model Provided Times Transport and Care about Heat to have Spice Circuit Simulation” , IEDMS , Taipei ,
91. S. C. Lin and you will J. B. Kuo, “Fringing-Triggered Barrier Reducing (FIBL) Outcomes of 100nm FD SOI NMOS Products with high Permittivity Door Dielectrics and you can LDD/Sidewall Oxide Spacer” , IEEE SOI Appointment Proc , Williamsburg ,
ninety-five. J. B. Kuo and S. C. Lin, “New Fringing Digital Field effect for the Brief-Channel Impression Tolerance Current out-of FD SOI NMOS Equipment which have LDD/Sidewall Oxide Spacer Build” , Hong kong Electron Equipment Fulfilling ,
93. C. L. Yang and you may J. B. Kuo, “High-Heat Quasi-Saturation Model of Higher-Current DMOS Stamina Gizmos” , Hong-kong Electron Devices Meeting ,
94. Elizabeth. Shen and you can J. B. Kuo, “0.8V CMOS Blogs-Addressable-Memories (CAM) Cell Ciurcuit with an instant Tag-Compare Abilities Using Vast majority PMOS Vibrant-Threshold (BP-DTMOS) Technique Based on Practical CMOS Technical for Low-Voltage VLSI Solutions” , In the world Symposium to your Circuits and you will Systems (ISCAS) Procedures , Arizona ,